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9209f-auto-06/14 features pwm and direction-controlled driving of four externally-powered nmos transistors a programmable dead time is included to avoid peak currents within the h-bridge integrated charge pump to provide gate vo ltages for high-side drivers and to supply the gate of the external battery reverse protection nmos 5v/3.3v regulator and current limitation function reset derived from 5v/3.3v regulator output voltage sleep mode with supply current of typically < 45a, wake-up by signal on pins en2 or on lin interface a programmable window watchdog battery overvoltage protection and battery undervoltage management overtemperature warning and protection (shutdown) lin 2.1 compliant 3.3v/5v regulator with trimmed band gap qfn32 package ata6823c h-bridge motor driver datasheet
ata6823c [datasheet] 9209f?auto?06/14 2 1. description the atmel ? ata6823c is designed for automotive body and powertrain applications. the ic is used to drive a continuous current motor in a full h-bridge configuratio n. an external microcontroller controls the driving function of the ic by providin g a pwm signal and a direction signal and allows the use of the ic in a motor-control applicatio n. the pwm control is performed by the low-side switch; the high-side switch is permanently on in the driving phase. the vmod e configuration pin can be set to 5v or 3.3v mode (for regulator and interface high le vel). the window watchdog has a programmable time, programmable by choosing a certain value of the external watchdog resist or rwd, internally trimmed to an accuracy of 10%. for communication a lin transceiver 2.1 is integrated. figure 1-1. block diagram vmode /reset microcontroller logic control vcc en1 wd 12v regulator vint 5v regulator otp 12 bit oscillator vcc 5v regulator bandgap charge pump hs driver 2 vres h2 cp cp cplo vbatsw vbat vbat battery vbg pbat vint vg cpih h1 m s1 s2 l2 vbat gnd dg3 en2 lin cc dg2 vcc pgnd l1 ot uv ov hs driver 1 r gate r gate r gate r gate ls driver 2 supervisor cc timer wd timer lin ls driver 1 dir tx rx pwm dg1
3 ata6823c [datasheet] 9209f?auto?06/14 2. pin configuration figure 2-1. pinning qfn32 note: yww date code (y = year - above 2000, ww = week number) ata6823 product name zzzzz wafer lot number al assembly sub-lot number table 2-1. pin description pin symbol i/o function 1 vmode i selector for v cc and interface logic voltage level 2 vint i/o blocking capacitor 220nf/10v/x7r 3 rwd i resistor defining the watchdog interval 4 cc i/o rc combination to adjust cross conduction time 5 /reset o reset signal for microcontroller 6 wd i watchdog trigger signal 7 gnd i ground for chip core 8 lin i/o lin-bus terminal 9 tx i transmit signal to lin bus from microcontroller 10 dir i defines the rotation direction for the motor 11 pwm i pwm input controls motor speed 12 en1 i microcontroller output to keep the chip in active mode 13 rx o receive signal from lin bus for microcontroller 14 dg3 o diagnostic output 3 15 dg2 o diagnostic output 2 16 dg1 o diagnostic output 1 17 s1 i/o source voltage h-bridge, high-side 1 18 h1 o gate voltage h-bridge, high-side 1 19 s2 i/o source voltage h-bridge, high-side 2 20 h2 o gate voltage h-bridge, high-side 2 21 vres i/o gate voltage for reverse protection nmos, blocking capacitor 470nf/25v/x7r vmode vint rwd cc /reset wd gnd lin vg cplo cphi vres h2 s2 h1 s1 en2 vbatsw vbat vcc pgnd l1 l2 pbat tx dir pwm en1 rx dg3 dg2 dg1 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 atmel yww ata6823c zzzzz-al
ata6823c [datasheet] 9209f?auto?06/14 4 22 cphi i charge pump capacitor 220nf/25v/x7r 23 cplo o 24 vg i/o blocking capacitor 470nf/25v/x7r 25 pbat i power supply (after reverse protection) for charge pump and h-bridge 26 l2 o gate voltage h-bridge, low-side 2 27 l1 o gate voltage h-bridge, low-side 1 28 pgnd i power ground for h-bridge and charge pump 29 vcc o 5v/100 ma supply for microcontroller, blocking capacitor 2.2f/10v/x7r 30 vbat i supply voltage for ic core (after reverse protection) 31 vbatsw o 100 pmos switch from v vbat 32 en2 i enable input table 2-1. pin description (continued) pin symbol i/o function
5 ata6823c [datasheet] 9209f?auto?06/14 3. functional description 3.1 power supply unit with supervisor functions 3.1.1 power supply the ic is supplied by a reverse-protected battery voltage. to prevent it from destruction, prope r external protection circuitry has to be added. it is recommended to use at least a capaci tor combination of storage and hf caps behind the reverse protection circuitry and closed to the vbat pin of the ic (see figure 1-1 on page 2 ). a fully-internal low-power and low-drop r egulator, stabilized by an external bloc king capacitor provides the necessary low- voltage supply needed for the wake-up process. the low-power band gap reference is trimmed and is used for the bigger vcc regulator, too. all internal blocks are supplied by the internal regulator. note: the internal supply voltage v int must not be used for any other supply purpose! nothing inside the ic except the logic interface to the microcontroller is supplied by the 5v/3.3v vcc regulator. a power-good comparator checks the output volt age of the v int regulator and keeps the whole chip in reset as long as the voltage is too low. there is a high-voltage switch which bri ngs out the battery voltage to the pin vbatsw for measurement purposes. this switch is switched on for vcc = high and stays on in case of a watchdog reset going to sleep mode, vbatsw turns off. the signal can be used to switch on external voltage regulators, etc. 3.1.2 voltage supervisor this block is intended to protect the ic and the external powe r mos transistors against overvo ltage on battery level and to manage undervoltage on it. function: in case of both overvoltage alarm (v thov ) and of undervoltage alarm (v thuv ) the external nmos motor bridge transistors will be switched off. the failure state will be flagged via dg2. no othe r actions will be carried out. the voltage supervision block is connected to vbat a nd filtered by a first-order low pass with a corner frequency of typical 15khz. 3.1.3 temperature supervisor there is a temperature sensor integrated on-chip to prevent the ic from overheating due to a failure in the external circuitry and to protect the external nmosfet transistors. in case of detected overtemperature (150c) , the diagnostic pin dg3 will be switched to ? h? to signalize this event to the microcontroller. it should undertake actions to reduce the power dissipation in the ic . in case of detected overtemperature (165c), the v cc regulator and all drivers including the lin transceiv er will be switched off im mediately and /reset will go low. both temperature thresholds are correlated. the absolute toler ance is 10c and there is a bu ilt-in hysteresis of about 10c to avoid fast oscillations. after cooling down below the 155c threshold; the ic will go into active mode. the lin interface has a separate thermal shutdown with disabled the low-side driv er at typically 165c. 3.2 sleep mode to be able to guarantee the low quiescent current of the inacti ve ic, a sleep mode is established. in sleep mode it is possible to wake-up the ic by us ing the pins en2 or lin. in sleep mode, the foll owing blocks are active: band gap internal 5v regulator (vint) with external blocking capacitor of 220nf input structure for detecting the en2 pins threshold wake-up block of the lin receive part
ata6823c [datasheet] 9209f?auto?06/14 6 3.3 wake-up and sleep mode strategy the ic has two modes: sleep and active. the change between the modes is described below. the default state after power-on is active mode. the wake-up procedure brings t he ic from a standby mode (sleep) to an active mo de (active). the internal 5v supply vint, the en2 pin input structure and a certain pa rt of the lin receiver are permanently active to ensu re a proper startup of the system. the go to active and go to sleep procedures are implemented as follows: go to active by activating pin en2 the input en2 is intended as a switch-on pin from an external si gnal. its input structure consists of a comparator with built-i n hysteresis. it is esd-protected by diodes against gnd and v vbat ; for this reason the input vo ltage level must be positive and not higher than v vbat . pulling the en2 pin up to the v vbat level will drive the ic into active mode. en2 is debounced with a time constant of 20s, based on a 100 khz clock. go to active using the lin interface the second possibility for wake-up can be performed using the li n transceiver. in sleep mode, the lin receiver is partially active. the wake-up by lin requires 2 steps: 1. if the voltage on pin lin is below a value of v /datwake (about v vbat ? 2v) the receive part of the lin interface is active (not to be confused with active mode of the whole ic ). the active receive part is able to detect a valid low on the lin pin. 2. if lin = low during a filter time t wakelin (typically 70s) the ic will change to active mode. a short change back to high during the filter time will reset the filter. this information is stored in a latch after entering active mode if the change to active mode was caused by lin, the en1 or en2 pins may remain low without disturbing the active mode. stay in active via en1 the input en1 is intended to keep the ic in active mode via a signal from the microcontroller. the input is esd-protected by diodes against gnd and vcc. therefore, the inpu t voltage must be positive and not higher than v cc . en1 cannot be used to switch from sleep to active because the v cc regulator is off in the sleep mode and v cc will be zero. go to sleep a high to low transition at pin en1 and a following permanent low for the time t gotosleep (typically 20s) switches the ic to sleep mode. figure 3-1 illustrates the wake- up by lin. the status prewake is characterize d by the activated rece ive block of the lin interface. after going to active mode, the v cc regulator starts working. go to sleep is possible with a valid high to low transition at pin en1 (pe rmanent low for longer than t db ) if en1 was in a valid high state (high for longer than t db ) before. switching characteristic of the outputs: when the ic is set to sleep mode by a ?high to low? transition at pin en1, the low-side transis tors of the external h-bridge are switched on for a short time. this causes a shortcircuit current pulse in the bridge because one of the high-side transistors is usually on. the pulse le ngth is similar to the one of the impl emented short circuit detection time t sc . for the selection of the external fets it needs to be considered that in the case of a short circuit condition the current in the transistors will flow for a time t sc with a maximum of 15s according to section 8. ?electrical characteristics? on page 15 , item 7.29. for the selection of the external fets this short circuit behavior has to be taken into consideration, so that they will not be damaged in the event of a short circuit condition caused by a failure or caused by the described sleep mode switching.
7 ata6823c [datasheet] 9209f?auto?06/14 figure 3-1. wake-up by pin lin 3.4 5v/3.3v vcc regulator the 5v/3.3v regulator is fully integrated on-chip. it requ ires only a 2.2f ceramic capacit or for stability and has 100ma current capability. using the vmod e pin, the output voltage can be selected to either 5v or 3.3v. switching of the output voltage during operation is not intended to be supported. the vmode pin must be hard-wired to either vint for 5v or to gnd for 3.3v. the logic high level of the microcontroller interface will be adapted to the vcc regulator voltage. the output voltage accuracy is in ge neral < 3%; in the 5v mode with v vbat < 9v it is limited to < 5%. to prevent destruction of the ic, the current delivered by the regulato r is limited to maximum 100ma to 350ma. the delivered voltage will break down and a reset may occur. please note that this regulator is the ma in heat source on the chip. the maximum output current at maximum battery voltage and high ambient temperature can onl y guaranteed if the ic is moun ted on an efficient heat sink. a power-good comparator checks the output voltage of the vcc re gulator and keeps the external microcontroller in reset as long as the voltage is too low. figure 3-2. correlation between vcc output voltage and reset threshold the voltage difference between the regulated output volta ge and the upper reset threshold voltage is higher than 75mv (vmode = high) and higher t han 50mv (vmode = low). sleep mode lin vcc en1 active mode active mode t w akelin = 70s regulator wake-up time t gotosleep = 20s v cc1-vthresh = v cc1 - v thresh 5.15v 4.9v 4.85v 4.1v v cc1 v thresh
ata6823c [datasheet] 9209f?auto?06/14 8 3.5 reset and watchdog management the timing basis of the watchdog is provided by the trimmed internal oscillator. its period t osc is adjustable via the external resistor r wd . the watchdog expects a triggering signal (a rising edge) from the microcontroller at the wd input within a period time window of t wd . in order to save current consumption, the watchdog is switched off during sleep mode. figure 3-3. timing diagram of the watchdog function 3.5.1 timing sequence for example, with an external resistor r wd =33k 1% we get the following typical parameters of the watchdog. t osc = 12.32s, t 1 = 12.1ms, t 2 = 9.61ms, t wd = 16.88ms 10% the times t res = 70ms and t d = 70ms are fixed values with a tolerance of 10%. after ramp-up of the battery voltage (power-on reset), the v cc regulator is switched on. th e reset output, /reset, stays low for the time t res (typically 70ms), then switches to high. for an initial lead time t d (typically 70ms for setups in the controller) the watchdog waits for a rising edge on wd to start its norma l window watchdog sequence. if no rising edge is detected, the watchdog will reset the microcontroller for t res and wait t d for the rising edge on wd. times t 1 (close window) and t 2 (open window) form the window watchdog sequence. to avoid receiving a reset from the watchdog, the triggering signal from the micr ocontroller must hit the time frame of t 2 = 9.61ms. the trigger event will restart the watchdog sequence. figure 3-4. t wd versus r wd if triggering fails, /reset will be pulled to ground for a shorte ned reset time of typically 2 ms. the watchdog start sequence is similar to the power-on reset. t 2 t 1 t 2 t 1 t d t d t resshort t res wd /reset rwd (k ) twd (ms) max min 0 10 20 30 40 50 60 10 20 30 40 50 60 70 80 90 100 typ
9 ata6823c [datasheet] 9209f?auto?06/14 the internal oscillator is trimmed to a tolerance of < 10%. this means that t 1 and t 2 can also vary by 10%. the following calculation shows the worst case ca lculation of the watchdog period t wd which the microcontroller has to provide. t 1min = 0.90 t 1 = 10.87ms, t 1max = 1.10 t 1 = 13.28ms t 2min = 0.90 t 2 = 8.65ms, t 2max = 1.10 t 2 = 10.57ms t wdmax = t 1min + t 2min = 10.87ms + 8.65ms = 19.52ms t wdmin = t 1max = 13.28ms t wd = 16.42ms 3.15ms (19.1%) figure 3-4 above shows the typical watchdog period t wd depending on the value of the external resistor r osc . a reset will be active for v cc < v thresx ; the level v thresx is realized with a hysteresis (hys resth ). 3.6 lin transceiver a bi-directional bus interface is implem ented for data transfer between the lin bus and the local lin pr otocol controller. the transceiver consists of a low side driver (1.2v at 40ma) wit h slew rate control, wave shap ing, current limitation, and a high-voltage comparator followed by a debouncing unit in the receiver. 3.6.1 transmit mode during transmission, the data at the pin tx will be transferre d to the bus driver to generate a bus signal on pin lin. to minimize the electromagnetic emission of the bus line, t he bus driver has an integrated slew rate control and wave- shaping unit. transmission will be interrupted in the following cases: thermal shutdown active or overtemperature lin active sleep mode figure 3-5. definition of bus timing parameters t bit th rec(min) th dom(min) th rec(max) thresholds of receiving node 2 thresholds of receiving node 1 th dom(max) t bus_dom(max) t bus_rec(min) t bus_dom(min) t rx_pdr(2) t rx_pdf(2) t rx_pdf(1) t rx_pdr(1) t bus_rec(max) t bit t bit v vbat (transceiver supply of transmitting node) rx (output of receiving node 2) rx (output of receiving node 1) tx lin bus signal (input to transmitting node)
ata6823c [datasheet] 9209f?auto?06/14 10 the recessive bus level is generated from the integrated 30k pull-up resistor in series with an active diode. this diode pre- vents the reverse current of vbus during differential voltage between vsup and bus (v bus >v sup ). no additional termination resistor is necessary to use the ata 6823c in lin slave nodes. if this ic is used for lin master nodes, it is necessary that the bus pin be terminated via an external 1 k resistor in series with a diode to vbat. 3.6.2 txd dominant time-out function the txd input has an internal pull-down resistor. an internal timer prevents the bus line from being driven permanently in dominant state. if txd is forced low longer than t dom > 18.4ms, the pin lin will be switched off to recessive mode. to reset this mode switch txd to high (> 10s) before switching lin to dominant again. 3.7 control inputs en1, en2, dir, pwm 3.7.1 pins en1, en2 any of the enable pins may be used to activate the ic with a high. en1 is a low level input, en2 can withstand a voltage up to 40v. internal pull-down resistors are included. 3.7.2 pin dir logical input to control the direction of the external motor to be controlled by the ic. an internal pull-down resistor is included. 3.7.3 pin pwm logical input for pwm information delivered by external micr ocontroller. duty cycle and frequency at this pin are passed through to the h-bridge. an inter nal pull-down resistor is included. the internal signal on is high when at least one valid trigger has been accepted (sync = 1) v vbat is inside the specified range (uv = 0 and nov = 1) the charge pump has reached its minimum voltage (cpok = 1) and the device is not overheated (ot2 = 0) in case of a short circuit, the appropriate transistor is swit ched off after a debounce time of about 10s. in order to avoid cross current through the bridge, a cross conduction timer is implemented. its time constant is programmable by means of an rc combination. table 3-1. status of the ic depending on control inputs and detected failures on dir pwm h1 l1 h2 l2 0 x x off off off off standby mode 1 0 pwm on off /pwm pwm motor pwm forward 1 1 pwm /pwm pwm on off motor pwm reverse
11 ata6823c [datasheet] 9209f?auto?06/14 in order to be able to distinguish between a wake-up from lin or from en2, the source of wake-up is flagged in dg1 until the first valid trigger (lin = 0, en2 = 1). 3.8 vg regulator the vg regulator is used to generate the ga te voltage for the low-side driver. its out put voltage will be used as one input for the charge pump, which generates the gate voltage for the high-side driver. the purpose of the regulator is to limit the gate voltage for the external power mos transistors to 12v. it needs a ceramic capacitor of 470nf for stability. the output voltage is reduced if the supply vo ltage at vbat falls below 12v. 3.9 charge pump the integrated charge pump is needed to supply the gates of the external power mos transistors. it needs a shuffle capacitor of 220nf and a reservoir capacit or of 470nf. without load, the output voltage on the reservoir capacitor is v vbat plus vg. the charge pump is clocked with a dedicated internal oscillator of 100khz. the charge pump is designed to reach a good emc level. 3.10 thermal shutdown there is a thermal shutdown block implemented. with rising ju nction temperature, a first wa rning level will be reached at 150c. at this point the ic stays fully fu nctional and a warning will be sent to the mi crocontroller. at junction temperature 165c the vcc regulator will be switched off and a reset occurs. 3.11 h-bridge driver the ic includes two push-pull drivers for control of two extern al power nmos used as high-side drivers and two push-pull drivers for control of two external power nmos used as low-si de drivers. the drivers are able to be used with standard and logic-level power nmos. the drivers for the high-side control use the charge pump voltage to supply the gates with a vo ltage of vg above the battery voltage level. the low-side drivers are supplied by vg directly . it is possible to control the external load (motor) in the forward and reverse direction (see table 3-1 on page 10 ). the duty cycle of the pmw cont rols the speed. a duty cycle of 100% is possible in both directions. table 3-2. status of the diagnostic outputs cpok ot1 ov uv sc dg1 dg2 dg3 0 x x x x ? 1 ? charge pump failure x 1 x x x ? ? 1 overtemperature warning x x 1 x x ? 1 ? overvoltage x x x 1 x ? 1 ? undervoltage x x x x 1 1 ? ? short circuit note: x represents: don't care ? no effect) ot1: overtemperature warning ov: overvoltage of vbat uv: undervoltage of vbat sc: short circuit cpok: charge pump ok
ata6823c [datasheet] 9209f?auto?06/14 12 3.11.1 cross conduction time to prevent high peak currents in the h-bridge, a non-overlappi ng phase for switching the external power nmos is realized. an external rc combination defines the cross conduction time in the following way: t cc (s) = 0.41 r cc (k ) c cc (nf) (tolerance: 5% 0.15s) the rc combination is charged to 5v and the switching leve l of the internal comparator is 67% of the start level. the resistor r cc must be greater than 5k and should be as close as possible to 10k , the c cc value has to be 5nf. use of cog capacitor material is recommended. the time measurement is triggered by the pwm or dir signal crossing the 50% level. figure 3-6. timing of the drivers the delays t hxlh and t lxlh include the cross conduction time t cc . 3.12 short circuit detection to detect a short in h-bridge circuitry, internal comparat ors detect the voltage difference between source and drain of the external power nmos. if the transistors are switched on and the source-drain voltage difference is higher than the value v sc (4v with tolerances) for a time > t sc (typically 10s) the signal sc (short ci rcuit) will be set and the drivers will be switched off immediately. the diagnostic pin dg1 will be set to ?h?. with the next transition on pin pwm, the bit will be cleared and the corresponding drivers, depending on the dir pin, will be switched on again. there is a pbat supervision block implemen ted to detect the possible voltage drop on pbat during a short circuit. if the voltage at pbat falls under v scpb (5.6v with tolerances) for a time > t sc the drivers will be switc hed off immediately and dg1 will be set to ?h?. it will be cleared as above. t lxlh t lxr t hxlh t hxr t cc t hxhl t hxf t lxhl t lxf t cc hx lx pwm or dir 80% 50% 20% 80% 20% t t t
13 ata6823c [datasheet] 9209f?auto?06/14 4. absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability . pin description pin name min. max. unit ground gnd 0 0 v power ground pgnd ?0.3 +0.3 v reverse protected battery voltage vbat +40 v reverse current out of pin vbat ?1 ma reverse protected battery voltage pbat +40 v reverse current out of pin pbat ?20 ma digital output /reset ?0.3 v vcc + 0.3 v digital output dg1, dg2, dg3 ?0.3 v vcc + 0.3 v 4.9v output, external blocking capacitor vint ?0.3 +5.5 v cross conduction time capaci tor/resistor combination cc ?0.3 v vint + 0.3 v digital input coming from microcontroller wd ?0.3 v vint + 0.3 v watchdog timing resistor rwd ?0.3 v vcc + 0.3 v digital input direction control dir ?0.3 v vcc + 0.3 v digital input pwm control + test mode pwm ?0.3 v vcc + 0.3 v digital input for enable control en1 ?0.3 v vcc + 0.3 v digital input for enable control en2 ?0.3 v vbat + 0.3 v 5v regulator output vcc ?0.3 +5.5 v digital input vmode ?0.3 v vint + 0.3 v 12v output, external blocking capacitor vg +16 v digital output rx ?0.3 v vcc + 0.3 v digital input tx ?0.3 v vcc + 0.3 v lin data pin lin ?27 v vbat + 2 v source external high-side nmos s1, s2 (?2) +40 (2) v gates external low-side nmos l1, l2 v pgnd ? 0.3 v vg + 0.3 v gates of external high-side nmos h1, h2 v sx ? 1 (1) v sx + 16 (1) v charge pump cplo v pbat + 0.3 v charge pump cphi v vres + 0.3 v charge pump output vres +40 (3) v switched vbat vbatsw ?0.3 v vbat + 0.3 v storage temperature ? store ?40 +150 c reverse current cplo, cphi, vg, vres, sx ?2 ma lx, hx ?1 ma notes: 1. x = 1.2 2. t < 0.5s 3. load dump of t < 0.5s tolerated
ata6823c [datasheet] 9209f?auto?06/14 14 5. thermal resistance parameters symbol value unit thermal resistance junction to heat slug r thjc <5 k/w thermal resistance junction to ambient when heat slug is soldered to pcb (1) r thja 29 k/w note: 1. thermal resistance junction ambient: 29k/w (at airflow of 0 lfpm), valid for jedec standard 4-layer thermal test board with 5 x 5 thermal via matrix (100m drill hole, filled vias). 6. operating range the operating conditions define the limits fo r functional operation and parametric char acteristics of the device. functionality outside these limits is not implied un less otherwise stated explicitly. parameters symbol min. max. unit operating supply voltage (1) v vbat1 v thuv v thov v operating supply voltage (2) v vbat2 6 v thuv v operating supply voltage (3) v vbat3 3 < 6 v operating supply voltage (4) v vbat4 0 < 3 v operating supply voltage (5) v vbat5 > v thov 40 v operating supply voltage (6) v vbat6 7 18 v normal functionality t j ?40 +150 c normal functionality, overtemperature warning t j 150 165 c drivers for h1, h2, l1, l2, and lin are switched off, vcc regulator is off t j 165 180 c note: 1. full functionality 2. h-bridge drivers are switched off (undervoltage detection) 3. h-bridge drivers are switched off, 5v/3.3v regulat or with reduced parameters, reset works correctly 4. h-bridge drivers are switched off, 5v regulator not workin g, reset not correct 5. h-bridge drivers are switched off 6. full lin functionality in confo rmance with lin specification 2.1 7. noise and surge imm unity, esd and latch-up parameters standard and test conditions value conducted interferences iso 7637-1 level 4 (1) conducted disturbances cisp25 level 5 esd according to ibee lin emc - pins lin, pbat, vbat - pin en2 (33 k serial resistor) test specification 1. 0 following iec 61000-4-2 6kv 5kv esd hbm with 1.5k /100pf esd- stm5.1-2001 jesd22-a114e 2007 cei/iec 60749-26: 2006 aec-q100-002-ref_d 3kv esd hbm with 1.5k /100pf pins en2, lin, pbat, vbat against gnd esd- stm5.1-2001 jesd22-a114e 2007 cei/iec 60749-26: 2006 aec-q100-002-ref_d 8kv esd cdm (field induced method) esd stm5.3.1 - 1999 1kv note: 1. test pulse 5: v bat max = 40v
15 ata6823c [datasheet] 9209f?auto?06/14 static latch-up tested according to aec-q100-004 and jesd78. 3 to 6 samples, 0 failures electrical post stress testing at room temperature in test, the volt age at the pins vbat, lin, cp, vbat sw, hx, and sx must not exceed 45v when not able to drive the specified current. 8. electrical characteristics all parameters given are valid for v thuv v vbat v thov and for ?40c ? ambient 125c unless stated otherwise. no. parameters test conditions pin symbol min. typ. max. unit type* 1 power supply and supervisor functions 1.1 current consumption v vbat v vbat = 13.5v (1) 25, 30 i vbat1 7 ma a 1.2 current consumption v vbat in standby mode v vbat =13.5v 25, 30 i vbat2 50 a a 1.3 internal power supply 2 v int 4.94 v a 1.4 band gap voltage 3 v bg 1.235 v a 1.5 overvoltage threshold up v vbat 30 v thov_up 21.2 22.7 v a 1.5.1 overvoltage threshold down v vbat 30 v thov_down 19.8 21.3 v a 1.6 overvoltage threshold hysteresis v vbat 30 v tovhys 1 2.4 v a 1.7 undervoltage threshold up v vbat 30 v thuv_up 6.8 7.4 v a 1.7.1 undervoltage threshold down v vbat 30 v thuv_down 6.5 7.0 v a 1.8 undervoltage threshold hysteresis v vbat measured during qualification only 30 v tuvhys 0.2 0.6 v a 1.9 on resistance of v vbat switch v vbat = 13.5v 31 r on_vbatsw 100 a 2 5v/3.3v regulator 2.1 regulated output voltage 9v < v vbat <40v i load = 0ma to 100ma 29 v cc1 4.85 (3.2) 5.15 (3.4) v a 2.2 regulated output voltage 6v < v vbat 9v i load = 0ma to 100ma 29 v cc2 4.75 (3.2) 5.25 (3.4) v a 2.3 line regulation i load = 0ma to 100ma 29 dc line regulation <1 50 mv a * type: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter notes: 1. en, dir, pwm = high 2. the use of x7r material is recommended 3. for higher values, stability at zero load is not guaranteed 4. tested during qualification only 5. value depends on t osc ; function tested with digital test pattern 6. tested during characterization only 7. supplied by charge pump 8. see section 3.11.1 ?cross conduction time? on page 12 9. voltage between source-drain of external switching transistors in active case 10. the short-circuit message will never be generated for switch-on time < t sc
ata6823c [datasheet] 9209f?auto?06/14 16 2.4 load regulation i load = 0ma to 100ma 29 dc load regulation <10 50 mv a 2.5 output current limitation v vbat > 6v 29 i os1 100 350 ma a 2.6 serial inductance to c vcc including pcb 29 esl 1 20 nh d 2.7 serial resistance to c vcc including pcb 29 esr 0 0.5 d 2.8 blocking cap at vcc (2), (3) 29 c vcc 1.1 3.3 f d 2.9 high threshold vmode 1 vmode h 4.0 v a 2.10 low threshold vmode 1 vmode l 0.7 v a 3 reset and watchdog 3.1 v cc threshold voltage level for /reset vmode = ?h? (vmode = ?l?) 29 v thresh 4.9 (3.25) v a 3.1a tracking of reset threshold with regulated output voltage vmode = ?h? (vmode = ?l?) 29 v vcc1-vthresh 75 (50) mv a 3.2 v cc threshold voltage level for /reset vmode = ?h? (vmode = ?l?) 29 v thresl 4.0 (2.65) v a 3.3 hysteresis of /reset level vmode = ?h? (vmode = ?l?)(4) 29 hys resth 70 200 600 (400) mv a 3.4 length of pulse at /reset pin (5) 5 t res 7000 t 100 a 3.5 length of short pulse at /reset pin (5) 5 t resshort 200 t 100 a 3.6 wait for the first wd trigger (5) 5 t d 7000 t 100 a 3.7 time for vcc < v thresl before activating /reset (4) 29 t delayresl 0.5 2 s c 3.8 resistor defining internal bias currents for watchdog oscillator 3 r rwd 10 91 k d 3.9 watchdog oscillator period r rwd = 33k 3 t osc 11.09 13.55 s a 3.11 watchdog input low-voltage threshold 6 v ilwd 0.3 v vcc v a 8. electrical characteristics (continued) all parameters given are valid for v thuv v vbat v thov and for ?40c ? ambient 125c unless stated otherwise. no. parameters test conditions pin symbol min. typ. max. unit type* * type: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter notes: 1. en, dir, pwm = high 2. the use of x7r material is recommended 3. for higher values, stability at zero load is not guaranteed 4. tested during qualification only 5. value depends on t osc ; function tested with digital test pattern 6. tested during characterization only 7. supplied by charge pump 8. see section 3.11.1 ?cross conduction time? on page 12 9. voltage between source-drain of external switching transistors in active case 10. the short-circuit message will never be generated for switch-on time < t sc
17 ata6823c [datasheet] 9209f?auto?06/14 3.12 watchdog input high-voltage threshold 6 v ihwd 0.7 v vcc v a 3.13 hysteresis of watchdog input voltage threshold 6 v hyswd 0.3 0.7 v a 3.14 close window (5) 6 t1 980 t osc a 3.15 open window (5) 6 t2 780 t osc a 3.16 output low-voltage of /reset at i olres = 1ma 5 v olres 0.4 v a 3.17 internal pull-up resistor at pin /reset 5 r pures 5 10 15 k a 4 lin transceiver, 7v v vbat 18v 4.1 low-level output current normal mode; v lin =0v, v rx =0.4v 13 il rxd 2 ma a 4.2 high-level output current normal mode; v lin =v vbat v rx =v cc ?0.4v 13 ih rxd 1 ma a 4.3 driver recessive output voltage r load = 1000 to vbat 8 v busrecdrv 0.9 v vbat v a 4.4 driver dominant voltage v busdom_drv_losup v vbat = 7.0v r load = 500 8 v _losup 1.2 v a 4.5 driver dominant voltage v busdom_drv_hisup v vbat = 18v r load = 500 8 v _hisup 2 v a 4.6 driver dominant voltage v busdom_drv_losup v vbat = 7.0v r load = 1000 8 v _losup_1k 0.6 v a 4.7 driver dominant voltage v busdom_drv_hisup v vbat = 18v r load = 1000 8 v _hisup_1k_ 0.8 v a 4.8a pull up resistor to v vbat serial diode required 8 r lin 20 47 k a 4.8b capacitance on lin pin to gnd 8 c lin 20 pf d 4.9 current limitation v bus = v vbat_max 8 i bus_lim 50 200 ma a 4.10 input leakage current at the receiver including pull- up resistor as specified input leakage current driver off v bus = 0v v vbat = 12v 8 i bus_pas_dom ?1 ma a 8. electrical characteristics (continued) all parameters given are valid for v thuv v vbat v thov and for ?40c ? ambient 125c unless stated otherwise. no. parameters test conditions pin symbol min. typ. max. unit type* * type: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter notes: 1. en, dir, pwm = high 2. the use of x7r material is recommended 3. for higher values, stability at zero load is not guaranteed 4. tested during qualification only 5. value depends on t osc ; function tested with digital test pattern 6. tested during characterization only 7. supplied by charge pump 8. see section 3.11.1 ?cross conduction time? on page 12 9. voltage between source-drain of external switching transistors in active case 10. the short-circuit message will never be generated for switch-on time < t sc
ata6823c [datasheet] 9209f?auto?06/14 18 4.11 leakage current lin recessive driver off 7v < v vbat < 18v 7v < v bus < 18v v bus = v vbat 8 i bus_pas_rec 20 a a 4.12 leakage current at ground loss control unit disconnected from ground loss of local ground must not affect communication in the residual network 7v < v vbat < 18v gnd device = v vbat v vbat = 12v 0v < v bus < 18v 8 i bus_no_gnd ?1 +1 ma a 4.13 node has to sustain the current that can flow under this condition. bus must remain operational under this condition 7v < v vbat < 18v v vbat disconnected v sup_device = gnd 0v < v bus < 18v 8 i bus 100 a a 4.14 center of receiver threshold 7v < v vbat < 18v v bus_cnt = (v th_dom +v th_rec )/2 8 v bus_cnt 0.475 v vbat 0.5 v vbat 0.525 v vbat v a 4.15 receiver dominant state 7v < v vbat < 18v v en = 5v 8 v busdom 0.4 v vbat v a 4.16 receiver recessive state 7v < v vbat < 18v v en = 5v 8 v busrec 0.6 v vbat v a 4.17 receiver input hysteresis 7v < v vbat < 18v v hys = v th_rec ? v th_dom 8 v bushys 0.175 v vbat v a 4.18 duty cycle 1 7v < v vbat < 18v th rec(max) =0.744 v vbat th dom(max) = 0.581 v vbat t bit = 50s d1 = t bus_rec(min) /(2 t bit ) load1: 1nf + 1k load2: 10nf + 500 8 d1 0.396 a 8. electrical characteristics (continued) all parameters given are valid for v thuv v vbat v thov and for ?40c ? ambient 125c unless stated otherwise. no. parameters test conditions pin symbol min. typ. max. unit type* * type: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter notes: 1. en, dir, pwm = high 2. the use of x7r material is recommended 3. for higher values, stability at zero load is not guaranteed 4. tested during qualification only 5. value depends on t osc ; function tested with digital test pattern 6. tested during characterization only 7. supplied by charge pump 8. see section 3.11.1 ?cross conduction time? on page 12 9. voltage between source-drain of external switching transistors in active case 10. the short-circuit message will never be generated for switch-on time < t sc
19 ata6823c [datasheet] 9209f?auto?06/14 4.19 duty cycle 2 7v < v vbat < 18v th rec(min) =0.422 v vbat th dom(min) = 0.284 v vbat t bit = 50s d2 = t bus_rec(max) /(2t bit ) load1: 1nf + 1k load2: 10nf + 500 8 d2 0.581 a 4.20 duty cycle 3 7v < v vbat < 18v th rec(max) =0.778 v vbat th dom(max) = 0.616 v vbat t bit = 96s d3 = t bus_rec(min) /(2 t bit ) load1: 1nf + 1k load2: 10nf + 500 8 d3 0.417 a 4.21 duty cycle 4 7v < v vbat < 18v th rec(min) =0.389 v vbat th dom(min) = 0.251 v vbat t bit = 96s d4 = t bus_rec(max) /(2 t bit ) load1: 1nf + 1k load2: 10nf + 500 8 d4 0.590 a 4.22 receiver propagation delay 7v < v vbat < 18v t rec_pd = max (t rx_pdr , t rx_pdf ) 13 t rx_pd 6 s a 4.23 symmetry of receiver propagation delay rising edge minus falling edge 7v < v vbat < 18v t rx_sym = t rx_pdr ? t rx_pdf 13 t rx_sym ?2 +2 s 4.24 dominant time for wake-up via lin-bus 7v < v vbat < 18v v lin = 0v 8 t bus 30 90 150 s a 5 control inputs en1, dir, pwm, wd, tx 5.1 input low-voltage threshold 12, 10, 11, 6, 9 v il 0.3 v vcc v a 5.2 input high-voltage threshold 12, 10, 11, 6, 9 v ih 0.7 v vcc v a 5.3 hysteresis 12, 10, 11, 6, 9 hys 0.3 0.5 0.7 v a 5.4 pull-down resistor en1, dir, pwm, wd 12, 10, 11, 6, r pd 25 50 100 k a 8. electrical characteristics (continued) all parameters given are valid for v thuv v vbat v thov and for ?40c ? ambient 125c unless stated otherwise. no. parameters test conditions pin symbol min. typ. max. unit type* * type: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter notes: 1. en, dir, pwm = high 2. the use of x7r material is recommended 3. for higher values, stability at zero load is not guaranteed 4. tested during qualification only 5. value depends on t osc ; function tested with digital test pattern 6. tested during characterization only 7. supplied by charge pump 8. see section 3.11.1 ?cross conduction time? on page 12 9. voltage between source-drain of external switching transistors in active case 10. the short-circuit message will never be generated for switch-on time < t sc
ata6823c [datasheet] 9209f?auto?06/14 20 5.5 pull-up resistor tx 9 r pu 25 50 100 k a 5.6 rise/fall time 12, 10, 11, 6, 9 t rf 100 ns d 5.7 debounce time en1 (6) 12 t db 2 t 100 3 t 100 s b 6 charge pump 6.1 charge pump voltage load = 0a 21 vcp v vbat + v vg v a 6.2 charge pump voltage load = 3ma, c cp = 100nf 21 vcp v vbat + v vg ? 1 v a 6.3 period charge pump oscillator 21 t 100 9 11 s a 6.4 cp load current in vg without cp load load = 0a 24 i vgcpz 0.6 ma a 6.5 cp load current in vg with cp load load = 3ma, c cp = 100nf 24 i vgcp 4 ma a 6.6 charge pump ok threshold up 21 v cpok_up 5.05 6.15 v a 6.7 charge pump ok threshold down 21 v cpok_down 4.25 5.35 v a 7 h-bridge driver 7.1 low-side driver high output voltage 26, 27 v lxh v vg ? 0.5v v vg v a 7.2 on-resistance of sink stage of pins l1, l2 26, 27 r dson_lxl, x = 1, 2 20 a 7.3 on-resistance of source stage of pins l1, l2 26, 27 r dson_lxh, x = 1, 2 20 a 7.4 output peak current at pins l1, l2, switched to low v lx = 3v 26, 27 i lxl, x = 1, 2 100 ma a 7.5 output peak current at pins l1, l2, switched to high v lx = 3v 26, 27 i lxh, x = 1, 2 ?100 ma a 7.6 pull-down resistance at pins l1, l2 26, 27 r pdlx x = 1, 2 30 140 k a 7.7 on-resistance of sink stage of pins h1, h2 v sx = 0 18, 20 r dson_hxl, x = 1, 2 20 a 8. electrical characteristics (continued) all parameters given are valid for v thuv v vbat v thov and for ?40c ? ambient 125c unless stated otherwise. no. parameters test conditions pin symbol min. typ. max. unit type* * type: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter notes: 1. en, dir, pwm = high 2. the use of x7r material is recommended 3. for higher values, stability at zero load is not guaranteed 4. tested during qualification only 5. value depends on t osc ; function tested with digital test pattern 6. tested during characterization only 7. supplied by charge pump 8. see section 3.11.1 ?cross conduction time? on page 12 9. voltage between source-drain of external switching transistors in active case 10. the short-circuit message will never be generated for switch-on time < t sc
21 ata6823c [datasheet] 9209f?auto?06/14 7.8 on-resistance of source stage of pins h1, h2 v sx = v vbat 18, 20 r dson_hxh, x = 1, 2 20 a 7.9 output peak current at pins hx, switched to low v vbat = 13.5v v sx = v vbat v hx = v vbat + 3v 18, 20 i hxl, x = 1, 2 100 ma a 7.10 output peak current at pins hx, switched to high v vbat = 13.5v v sx = v vbat v hx = v vbat + 3v 18, 20 i hxh, x = 1, 2 ?100 ma a 7.11 static switch output low voltage at pins hx and lx v sx = 0v i hx = 1ma i lx = 1ma 18, 20, 26, 27 v hxl , v lxl x = 1, 2 0.3 v a 7.12 static high-side switch output high-voltage pins h1, h2 i lx = ?10a (pwm = static) 18, 20 v hxhstat1 (7) v vbat + v vg ? 1 v vbat + v vg v a 7.13 sink resistance between hx and sx v vbat = v pbat = 9v, i_vg = ?20ma 17, 18, 19, 20 r pdhx 30 150 k a dynamic parameters 7.15 propagation delay time, low-side driver from high to low figure 3-6 on page 12 v vbat = 13.5v 26, 27 t lxhl 0.5 s a 7.16 propagation delay time, low-side driver from low to high v vbat = 13.5v 26, 27 t lxlh 0.5 + t cc s a 7.17 fall time low-side driver v vbat = 13.5v c gx = 5nf 26, 27 t lxf 0.5 s a 7.18 rise time low-side driver v vbat = 13.5v 26, 27 t lxr 0.5 s a 7.19 propagation delay time, high-side driver from high to low figure 3-6 on page 12 v vbat = 13.5v 18, 20 t hxhl 0.5 s a 7.20 propagation delay time, high-side driver from low to high v vbat = 13.5v 18, 20 t hxlh 0.5 + t cc s a 7.21 fall time high-side driver v vbat = 13.5v, c gx = 5nf 18, 20 t hxf 0.5 s a 7.22 rise time high-side driver v vbat = 13.5v 18, 20 t hxr 0.5 s a 7.23 cross conduction time r cc = 10k , c cc = 1nf(8) 4 t cc 3.75 4.45 s a 8. electrical characteristics (continued) all parameters given are valid for v thuv v vbat v thov and for ?40c ? ambient 125c unless stated otherwise. no. parameters test conditions pin symbol min. typ. max. unit type* * type: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter notes: 1. en, dir, pwm = high 2. the use of x7r material is recommended 3. for higher values, stability at zero load is not guaranteed 4. tested during qualification only 5. value depends on t osc ; function tested with digital test pattern 6. tested during characterization only 7. supplied by charge pump 8. see section 3.11.1 ?cross conduction time? on page 12 9. voltage between source-drain of external switching transistors in active case 10. the short-circuit message will never be generated for switch-on time < t sc
ata6823c [datasheet] 9209f?auto?06/14 22 7.24 external resistor 4 r cc 5 k d 7.25 external capacitor 4 c cc 5 nf d 7.26 r on of t cc switching transistor 4 r oncc 200 a 7.28 short circuit detection voltage (9) 17, 19 v sc 3.5 4 4.7 v a 7.29 short circuit detection time (10) 17, 19 t sc 5 10 15 s a 7.30 vg regulator output voltage v vbat = v pbat = 18v, i_vg = ?20ma 24 v vg 11 14 v a 7.31 vg regulator output voltage switch mode v vbat = v pbat = 9v, i_vg = ?20ma 24 v vgswitch 7 9 v a 8 input en2 8.1 input low-voltage threshold 32 v il 2.3 3.6 v a 8.2 input high-voltage threshold 32 v ih 2.8 4.0 v a 8.3 hysteresis (6) 32 hys 0.47 v a 8.4 pull-down resistor 32 r pd 50 100 200 k a 8.5 rise/fall time 32 t rf 100 ns d 8.6 debounce time (6) 32 t db 2 t 100 3 t 100 s b 9 diagnostic outputs dg1, dg2, dg3 9.1 low level output current v dg = 0.4v (6) 15, 16 il 2 ma a 9.2 high level output current v dg = vcc ? 0.4v (6) 15, 16 ih 1 ma a 8. electrical characteristics (continued) all parameters given are valid for v thuv v vbat v thov and for ?40c ? ambient 125c unless stated otherwise. no. parameters test conditions pin symbol min. typ. max. unit type* * type: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter notes: 1. en, dir, pwm = high 2. the use of x7r material is recommended 3. for higher values, stability at zero load is not guaranteed 4. tested during qualification only 5. value depends on t osc ; function tested with digital test pattern 6. tested during characterization only 7. supplied by charge pump 8. see section 3.11.1 ?cross conduction time? on page 12 9. voltage between source-drain of external switching transistors in active case 10. the short-circuit message will never be generated for switch-on time < t sc
23 ata6823c [datasheet] 9209f?auto?06/14 9. application 9.1 general remark this section describes the principal application for which the ata6823c was designed. because atmel ? cannot be considered to understand fully all aspects of the system, app lication, and environment, no warranties of fitness for a particular purpose are given. 10. errata 10.1 faulty pulse at dg1 a faulty pulse of approximately 100ns appears at pin 16 (dg1), signalizing short circuit condition, under following circumstances: general condition: pwm = high and detected undervo ltage of vbat (signaliz ed at pin 15 = dg2) or detected overvoltage of vbat (signalized at pin 15 = dg2) or detected undervoltage of the charge pump (signalized at pin 15 = dg2) or overtemperature shutdown. 10.2 problem fix/workaround set the software to ignore the faulty pulse. table 9-1. typical ex ternal co mponents component function value tolerance c vint blocking capacitor at vint 220nf, 10v, x7r 50% c vcc blocking capacitor at vcc 2.2f, 10v, x7r 50% c cc cross conduction time definition capacitor typical 330pf, 100v, cog r cc cross conduction time definition resistor typical 10k c vg blocking capacitor at vg typical 470nf, 25v, x7r 50% c cp charge pump capacitor typical 220nf, 25v, x7r c vres reservoir capacitor typical 470nf, 25v, x7r r rwd watchdog time definition resistor typical 51k r linex pull-up resistor for lin bus (master only) typical 1k c linex filter capacitor for lin bus typical 220pf, 100v
ata6823c [datasheet] 9209f?auto?06/14 24 12. package information 11. ordering information extended type number package remarks ata6823c-phqw qfn32 pb-free package drawing contact: packagedrawings@atmel.com gpc drawing no. rev. title 6.543-5097.01-4 1 02/24/03 package: qfn32_7x7 exposed pad 4.7x4.7 specifications according to din technical drawings dimensions in mm not indicated tolerances 0.05 32 25 9 16 17 24 8 1 32 8 1 7 4.55 0.65 nom. 4.7 0.3 0.6 0.9 0.1 0.05 -0.05 +0
25 ata6823c [datasheet] 9209f?auto?06/14 13. revision history please note that the following page numbers re ferred to in this section re fer to the specific revision mentioned, not to this document. revision no. history 9209f-auto-06/14 ? put datasheet in the latest template 9209e-auto-03/12 ? section 4 ?absolute maximum ratings? on page 13 changed 9209d-auto-11/11 ? figure 3-5 ?definition of bus timi ng parameters? on page 10 changed ? section 4 ?absolute maximum ratings? on page 15 changed ? section 8 ?electrical characteristics? numbers 4.8 and 4.12 on pages 19 to 20 changed 9209c-auto-01/11 ? section 3.3 ?wake-up and sleep mode strategy? on page 7 changed 9209b-auto-11/10 ? section 8 ?electrical characteristics? number 4.8b on page 19 added ? table 9-1 ?typical external components? on page 25 changed
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